[PATCH] efi-entry.S: add dsb and isb
mark.rutland at arm.com
Wed Nov 12 08:58:42 PST 2014
I've Cc'd a few people who were involved in authoring this.
I have an alternative patch  that also adds some missing maintenance.
Would you be able to give that a go?
On Tue, Nov 11, 2014 at 06:32:04AM +0000, Joel Schopp wrote:
> Add a dsb and isb after the instruction flush before the data cache and
> mm offing. Without this patch I am seeing synchronous exceptions occur
> every few boots.
> Signed-off-by: Joel Schopp <joel.schopp at amd.com>
> Tested-by: Tom Lendacky <Thomas.Lendacky at amd.com>
> arch/arm64/kernel/efi-entry.S | 6 ++++++
> 1 file changed, 6 insertions(+)
> diff --git a/arch/arm64/kernel/efi-entry.S b/arch/arm64/kernel/efi-entry.S
> index 619b1dd..7d95eda 100644
> --- a/arch/arm64/kernel/efi-entry.S
> +++ b/arch/arm64/kernel/efi-entry.S
> @@ -76,6 +76,12 @@ ENTRY(efi_stub_entry)
> bl __flush_dcache_area
> ic ialluis
> + /* We need to sync again after the instruction cache sync
> + * and before turning off the dcache and mmu
> + */
> + dsb sy
> + isb
In my series I reasoned that it wasn't necessary to have an ISB before
we disabled the MMU. The current image must already be visible to the
I-cache, so the I-cache can't have stale entries for it. We don't
disable the MMU until after the image is visible at the PoC, so we
shouldn't break the visbility of the current image to the I-cache.
There is a bug in that We don't flush the current image in case of
relocation, but I don't see how the ISB would help there.
> /* Turn off Dcache and MMU */
> mrs x0, CurrentEL
> cmp x0, #CurrentEL_EL2
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