[PATCH] ARM: Don't ever downscale loops_per_jiffy in SMP systems#
swarren at wwwdotorg.org
Tue May 13 15:15:43 PDT 2014
On 05/13/2014 03:50 PM, Doug Anderson wrote:
> ...but then I found the true problem shows up when we transition
> between very low frequencies on exynos, like between 200MHz and
> 300MHz. While transitioning between frequencies the system
> temporarily bumps over to the "switcher" PLL running at 800MHz while
> waiting for the main PLL to stabilize. No CPUFREQ notification is
> sent for that. That means there's a period of time when we're running
> at 800MHz but loops_per_jiffy is calibrated at between 200MHz and
> I'm welcome to any suggestions for how to address this. It sorta
> feels like it would be a common thing to have a temporary PLL during
> the transition, ...
We definitely do that on Tegra for some cpufreq transitions.
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