[PATCH 68/97] ARM: l2c: sti: remove cache size override

Srinivas Kandagatla srinivas.kandagatla at linaro.org
Fri May 9 09:10:22 PDT 2014

Hi Maxime,
On 09/05/14 07:53, Maxime Coquelin wrote:
> Hi Srini,
> On 04/29/2014 08:48 AM, Srinivas Kandagatla wrote:
>> Hi Russell,
>> Thankyou for the patch,
>> The only issue I see is, on most of the STi SOCs the default value for
>> AUXCTRL register is 0x0, so the waysize is not set.
> I checked all the ARM SoCs we support currently.
> Only STiH416 has its reset value at 0x0.
>> The way size is different on some SOCs in the same series.
>> Where is the way-size mentioned in this new style?
> Then, I think it should be the role of the bootloaders to set it for
> STiH416 (I have been told U-Boot already does it).
> Does it sound acceptable for you?

That's great, so the gdb startup scripts should takecare of it too.


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