[PATCH 06/17] pci: host: pcie-designware: Use *base-mask* for configuring the iATU
jg1.han at samsung.com
Thu May 8 02:05:11 PDT 2014
On Tuesday, May 06, 2014 10:59 PM, Arnd Bergmann wrote:
> On Tuesday 06 May 2014 19:03:52 Kishon Vijay Abraham I wrote:
> > In DRA7, the cpu sees 32bit address, but the pcie controller can see only 28bit
> > address. So whenever the cpu issues a read/write request, the 4 most
> > significant bits are used by L3 to determine the target controller.
> > For example, the cpu reserves 0x2000_0000 - 0x2FFF_FFFF for PCIe controller but
> > the PCIe controller will see only (0x000_0000 - 0xFFF_FFF). So for programming
> > the outbound translation window the *base* should be programmed as 0x000_0000.
> > Whenever we try to write to say 0x2000_0000, it will be translated to whatever
> > we have programmed in the translation window with base as 0x000_0000.
> > Cc: Bjorn Helgaas <bhelgaas at google.com>
> > Cc: Marek Vasut <marex at denx.de>
> > Signed-off-by: Kishon Vijay Abraham I <kishon at ti.com>
> > Acked-by: Jingoo Han <jg1.han at samsung.com>
> > Acked-by: Mohit Kumar <mohit.kumar at st.com>
> Sorry, but NAK.
> We have a standard 'dma-ranges' property to handle this, so use it.
> See the x-gene PCIe driver patches for an example. Please also talk
> to Santosh about it, as he is implementing generic support for
> parsing dma-ranges in platform devices at the moment.
Do you mean the following patch?
> I also suspect you will have to implement swiotlb support to make
> generic PCI devices work behind this bridge. Otherwise you end up
> with random physical addresses passed into DMA registers.
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