*READ THIS IF YOUR SOC HAS A L2 CACHE* PL310 auxctrl settings

[Russell King - ARM Linux]

On Fri, Mar 28, 2014 at 01:51:27PM +0100, Maxime Coquelin wrote:
> On 03/18/2014 12:22 PM, Russell King - ARM Linux wrote:
>> arch/arm/mach-sti/board-dt.c:                           Y  30480000 c0000fff
>
> For STiH416 SoC, the reset value of the AUX_CTRL register is 0x02000000.
> So bits 19:17 = 0, whereas the expected value is bits 19:17 = 4.

Which L2 cache is it?  210/220/310 ?

Thanks.

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