[PATCH RFC 5/6] ARM: zynq: DT: Migrate UART to Cadence binding
Soren Brinkmann
soren.brinkmann at xilinx.com
Tue Mar 4 12:17:28 EST 2014
The Zynq UART is Cadence IP and the driver has been renamed accordingly.
Migrate the DT to use the new binding for the UART driver.
Signed-off-by: Soren Brinkmann <soren.brinkmann at xilinx.com>
Acked-by: Peter Crosthwaite <peter.crosthwaite at xilinx.com>
---
arch/arm/boot/dts/zynq-7000.dtsi | 8 ++++----
1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/zynq-7000.dtsi b/arch/arm/boot/dts/zynq-7000.dtsi
index 8b67b19392ec..a229a14834ce 100644
--- a/arch/arm/boot/dts/zynq-7000.dtsi
+++ b/arch/arm/boot/dts/zynq-7000.dtsi
@@ -67,19 +67,19 @@
};
uart0: uart at e0000000 {
- compatible = "xlnx,xuartps";
+ compatible = "cdns,uart-r1p8";
status = "disabled";
clocks = <&clkc 23>, <&clkc 40>;
- clock-names = "ref_clk", "aper_clk";
+ clock-names = "uart_clk", "pclk";
reg = <0xE0000000 0x1000>;
interrupts = <0 27 4>;
};
uart1: uart at e0001000 {
- compatible = "xlnx,xuartps";
+ compatible = "cdns,uart-r1p8";
status = "disabled";
clocks = <&clkc 24>, <&clkc 41>;
- clock-names = "ref_clk", "aper_clk";
+ clock-names = "uart_clk", "pclk";
reg = <0xE0001000 0x1000>;
interrupts = <0 50 4>;
};
--
1.9.0.1.g4196000
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