[PATCH] clk: socfpga: Add a second parent option for the dbg_base_clk

[Dinh Nguyen]

Hi Mike,

On 6/13/14 9:21 PM, dinguyen at altera.com wrote:
> From: Dinh Nguyen <dinguyen at altera.com>
>
> The debug base clock can be bypassed from the main PLL to the OSC1 clock.
> The bypass register is the staysoc1(0x10) register that is in the clock
> manager.
>
> This patch adds the option to get the correct parent for the debug base
> clock.
>
> Signed-off-by: Dinh Nguyen <dinguyen at altera.com>
> ---
>  arch/arm/boot/dts/socfpga.dtsi   |    2 +-
>  drivers/clk/socfpga/clk-periph.c |    9 +++++++++
>  drivers/clk/socfpga/clk.h        |    1 +
>  3 files changed, 11 insertions(+), 1 deletion(-)
>
>
Please dis-regard this patch. I forgot to update the socfpga_periph_init()
function to support having multiple parents. I'll send a v2 shortly.

Sorry for the noise.

Dinh