[PATCH v7 2/6] clk: samsung: register exynos5420 apll/kpll configuration data

[Tomasz Figa]

On 14.07.2014 15:38, Thomas Abraham wrote:
> From: Thomas Abraham <thomas.ab at samsung.com>
> 
> Register the PLL configuration data for APLL and KPLL on Exynos5420. This
> configuration data table specifies PLL coefficients for supported PLL
> clock speeds when a 24MHz clock is supplied as the input clock source
> for these PLLs.
> 
> Cc: Tomasz Figa <t.figa at samsung.com>
> Signed-off-by: Thomas Abraham <thomas.ab at samsung.com>
> Reviewed-by: Amit Daniel Kachhap <amit.daniel at samsung.com>
> Tested-by: Arjun K.V <arjun.kv at samsung.com>
> ---
>  drivers/clk/samsung/clk-exynos5420.c |   28 ++++++++++++++++++++++++++++
>  1 file changed, 28 insertions(+)
> 

Looks good. Will apply.

Best regards,
Tomasz