[PATCH v6 4/5] PCI: add PCI controller for keystone PCIe h/w

[Rob Herring]

On Fri, Jul 18, 2014 at 10:14 AM, Murali Karicheri <m-karicheri2 at ti.com> wrote:
> keystone PCIe controller is based on v3.65 version of the
> designware h/w. Main differences are
>         1. No ATU support
>         2. Legacy and MSI irq functions are implemented in
>            application register space
>         3. MSI interrupts are multiplexed over 8 IRQ lines to the Host
>            side.
> All of the Application register space handing code are organized into
> pci-keystone-dw.c and the functions are called from pci-keystone.c
> to implement PCI controller driver. Also add necessary DT documentation
> for the driver.
>
> Signed-off-by: Murali Karicheri <m-karicheri2 at ti.com>
> Acked-by: Santosh Shilimkar <santosh.shilimkar at ti.com>
>
> CC: Russell King <linux at arm.linux.org.uk>
> CC: Grant Likely <grant.likely at linaro.org>
> CC: Rob Herring <robh+dt at kernel.org>
> CC: Mohit Kumar <mohit.kumar at st.com>
> CC: Jingoo Han <jg1.han at samsung.com>
> CC: Bjorn Helgaas <bhelgaas at google.com>
> CC: Pratyush Anand <pratyush.anand at st.com>
> CC: Richard Zhu <r65037 at freescale.com>
> CC: Kishon Vijay Abraham I <kishon at ti.com>
> CC: Marek Vasut <marex at denx.de>
> CC: Arnd Bergmann <arnd at arndb.de>
> CC: Pawel Moll <pawel.moll at arm.com>
> CC: Mark Rutland <mark.rutland at arm.com>
> CC: Ian Campbell <ijc+devicetree at hellion.org.uk>
> CC: Kumar Gala <galak at codeaurora.org>
> CC: Randy Dunlap <rdunlap at infradead.org>
> CC: Grant Likely <grant.likely at linaro.org>
> ---
>  .../devicetree/bindings/pci/pci-keystone.txt       |   71 +++
>  drivers/pci/host/Kconfig                           |    5 +
>  drivers/pci/host/Makefile                          |    1 +
>  drivers/pci/host/pci-keystone-dw.c                 |  516 ++++++++++++++++++++
>  drivers/pci/host/pci-keystone.c                    |  385 +++++++++++++++
>  drivers/pci/host/pci-keystone.h                    |   59 +++
>  6 files changed, 1037 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/pci/pci-keystone.txt
>  create mode 100644 drivers/pci/host/pci-keystone-dw.c
>  create mode 100644 drivers/pci/host/pci-keystone.c
>  create mode 100644 drivers/pci/host/pci-keystone.h
>
> diff --git a/Documentation/devicetree/bindings/pci/pci-keystone.txt b/Documentation/devicetree/bindings/pci/pci-keystone.txt
> new file mode 100644
> index 0000000..9c96164
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/pci/pci-keystone.txt
> @@ -0,0 +1,71 @@
> +TI Keystone PCIe interface
> +
> +Keystone PCI host Controller is based on Designware PCI h/w version 3.65.
> +It shares common functions with PCIE Designware core driver and inherit
> +common properties defined in
> +Documentation/devicetree/bindings/pci/designware-pci.txt
> +
> +Please refer to Documentation/devicetree/bindings/pci/designware-pci.txt
> +for the details of designware DT bindings. Additional properties are
> +described here as well propeties that are not applicable.
> +
> +Required Properties:-
> +
> +compatibility: "ti,keystone-pcie"
> +reg:   index 1 is the base address and length of DW application registers.
> +       index 2 is the base address and length of PCI mode configuration
> +       register.
> +       index 3 is the base address and length of PCI device ID register.
> +
> +pcie_msi_intc : Interrupt controller device node for MSI irq chip
> +       interrupt-cells: should be set to 1
> +       interrupt-parent: Parent interrupt controller phandle
> +       interrupts: GIC interrupt lines connected to PCI MSI interrupt lines
> +
> + Example:
> +       pcie_msi_intc: msi-interrupt-controller {
> +                       interrupt-controller;
> +                       #interrupt-cells = <1>;
> +                       interrupt-parent = <&gic>;
> +                       interrupts = <GIC_SPI 30 IRQ_TYPE_EDGE_RISING>,
> +                                       <GIC_SPI 31 IRQ_TYPE_EDGE_RISING>,
> +                                       <GIC_SPI 32 IRQ_TYPE_EDGE_RISING>,
> +                                       <GIC_SPI 33 IRQ_TYPE_EDGE_RISING>,
> +                                       <GIC_SPI 34 IRQ_TYPE_EDGE_RISING>,
> +                                       <GIC_SPI 35 IRQ_TYPE_EDGE_RISING>,
> +                                       <GIC_SPI 36 IRQ_TYPE_EDGE_RISING>,
> +                                       <GIC_SPI 37 IRQ_TYPE_EDGE_RISING>;
> +       };
> +
> +pcie_intc: Interrupt controller device node for Legacy irq chip
> +       interrupt-cells: should be set to 1
> +       interrupt-parent: Parent interrupt controller phandle
> +       interrupts: GIC interrupt lines connected to PCI Legacy interrupt lines
> +
> + Example:
> +       pcie_intc: legacy-interrupt-controller {
> +               interrupt-controller;
> +               #interrupt-cells = <1>;
> +               interrupt-parent = <&gic>;
> +               interrupts = <GIC_SPI 26 IRQ_TYPE_EDGE_RISING>,
> +                       <GIC_SPI 27 IRQ_TYPE_EDGE_RISING>,
> +                       <GIC_SPI 28 IRQ_TYPE_EDGE_RISING>,
> +                       <GIC_SPI 29 IRQ_TYPE_EDGE_RISING>;
> +       };

This seems wrong. Legacy interrupts should be described with
interrupt-map and then PCI child devices have a standard interrupt
specifier.

I'm not sure about MSIs, but I would think they would have a standard
format too.

> +
> +Optional properties:-
> +       phys: phandle to Generic Keystone SerDes phy for PCI
> +       phy-names: name of the Generic Keystine SerDes phy for PCI
> +         - If boot loader already does PCI link establishment, then phys and
> +           phy-names shouldn't be present.
> +       ti,enable-linktrain - Enable Link training.
> +         - If boot loader already does PCI link establishment, then this
> +           shouldn't be present.

Can't you read from the h/w if the link is trained?

Rob