iMX6Q FEC: transmit queue 0 timed out

[Holger Schurig]

Andy,

to revive an old thread: I now got ethernet working. Basically, I
needed to set the system so that the PHY is generating the ref-clock.
I found even code in arch/arm/mach-imx/mach-imx6q.c that controls
setting of GPR1[21] from the device tree. However, I wasn't really
able to come up with a device-tree that triggers the code
IMX6Q_GPR1_ENET_CLK_SEL_PAD. For example, Neither
Documentation/devicetree/bindings/net/fsl-fec.txt nor any other file
there mention anything on how to do this.

Currently I disable the 3rd clock. I changed the default
         clocks = <&clks 117>, <&clks 117>, <&clks 190>;
         clock-names = "ipg", "ahb", "ptp";
(from imx6qdl.dtsi) to my dts:
         clocks = <&clks 117>, <&clks 117>;
         clock-names = "ipg", "ahb";

Would I have needed to create some dummy clock, e.g. "ext-phy-clk" and
specified that as a third clock in my dts?


Russel,

the 8720A PHY is configured for int/ext clock via it's nINTSEL pin.
And our hardware designers put that pin to a LED, so I cannot
influence it from the IOMUXC function block of the CPU. Thanks for the
idea anyway, maybe someone else finds this in google :-)