[PATCH v3 0/3] ARM: sun7i/sun6i: irqchip: Irqchip driver for NMI

[Carlo Caione]

On Sat, Jan 11, 2014 at 4:19 PM, Carlo Caione <carlo.caione at gmail.com> wrote:
> Allwinner A20/A31 SoCs have a special interrupt controller for managing NMI.
> Three register are present to (un)mask, control and acknowledge NMI.
> These two patches add a new irqchip driver in cascade with GIC.
>
> Changes since v1:
>         - added binding document
>
> Changes since v2:
>         - fixed trigger type in DTS
>         - new explanations in binding documentation
>         - added support for A31 (sun6i)

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