[PATCH v2 1/2] spi:fsl-dspi:add support of DSPI IP in big endian

[Mark Brown]

On Wed, Jan 08, 2014 at 02:14:14PM +0800, Chao Fu wrote:

This looks a lot nicer - a few things below though.

> +#define DSPI_BITWISE16(d, v)	(d->big_endian ? cpu_to_be16(v) : cpu_to_le16(v))
> +#define DSPI_BITWISE32(d, v)	(d->big_endian ? cpu_to_be32(v) : cpu_to_le32(v))

These should probably be inline for the same reason as the I/O
functions, perhaps even being done as part of the I/O functions.

> +static inline u16 dspi_readw(void __iomem *addr)
> +{
> +	u16 __v = (__force u16) __raw_readw(addr);
> +	__iormb();
> +
> +	return __v;
> +}

Why does this need a barrier and why does it not take care of the
endianness translation?  A quick glance through shows most if not all of
the callers doing the translation.

> +static inline void dspi_writew(u16 val, void __iomem *addr)
> +{
> +	__iowmb();
> +	__raw_writew((__force u16) val, addr);
> +}

Again the memory barrier seems odd, especially the barrier *before*
doing the write.
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