L1 & L2 cache flush sequence on CortexA5 MPcore w.r.t low power modes

[Lorenzo Pieralisi]

On Tue, Dec 24, 2013 at 05:52:48PM +0000, Antti Miettinen wrote:
> Sorry to still bring up an old thread, but this still bothers me..
> 
> Lorenzo Pieralisi <lorenzo.pieralisi at arm.com> writes:
> > [..] dirty cache lines can be migrated across
> > processors caches. [..]
> 
> What are the conditions under which this can happen? Which CPUs in
> reality migrate dirty lines between caches? And C==0 does prevent
> migrations as well as local allocations?

It happens if a cache miss is for a cache line that is dirty on another CPU
that is part of the coherency domain, the line is just moved from one L1
to the local L1.

Yes, C bit cleared prevents allocations so it prevents migrations too.

Lorenzo