[PATCH 1/3] ARM: imx6sx: Set PLL2 as parent of QSPI clocks

[Fabio Estevam]

Hi Shawn,

On Tue, Dec 16, 2014 at 5:29 AM, Shawn Guo <shawn.guo at linaro.org> wrote:

> What is the original parent clock, and how does that cause a division by
> zero error?

The default qspi2_clk_sel contains '110' which is marked as 'reserved'
in the reference manual.

This causes the qspi2 to look like this in the clock tree:

 dummy                                    4            4           0          0
    qspi2_sel                             1            1           0          0
       qspi2_pred                         1            1           0          0
          qspi2_podf                      1            1           0          0
             gpmi_io                      0            0           0          0
             qspi2                        1            1           0

A 'dummy' clock gets assigned as parent.

This is will cause the division by zero when the qspi driver calls
clk_set_rate().

I will send a v2 with such explanation.