[PATCH v2 2/3] i2c: cadence: Set the hardware time-out register to maximum value

[Wolfram Sang]

On Wed, Dec 03, 2014 at 06:05:25PM +0530, Harini Katakam wrote:
> From: Vishnu Motghare <vishnum at xilinx.com>
> 
> Cadence I2C controller has bug wherein it generates invalid read transactions
> after timeout in master receiver mode. This driver does not use the HW
> timeout and this interrupt is disabled but the feature itself cannot be
> disabled. Hence, this patch writes the maximum value (0xFF) to this register.
> This is one of the workarounds to this bug and it will not avoid the issue
> completely but reduces the chances of error.
> 
> Signed-off-by: Vishnu Motghare <vishnum at xilinx.com>
> Signed-off-by: Harini Katakam <harinik at xilinx.com>

Applied to for-current, thanks!

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