[PATCH 03/12] irqchip: gic: define register_routable_domain_ops conditional

[Stefan Agner]

On 2014-12-03 20:04, Marc Zyngier wrote:
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>> What do you mean by the shared state in the drawing above? Currently, I
>> check whether a interrupt is already used by the other core by reading
>> the register (do this configuration register reflect the "shared state"
>> in your drawing?).
> 
> I think that is basically it. It should only be the register that
> decides on the actual routing. BTW, how do you arbitrate between
> concurrent accesses to this register? Or is only the A5 allowed to
> change it?
 
No arbitration so far... The whole Vybrid on M4 stuff is quite a hack
right now. For instance also the concurrent access to the clock
registers is not handled. Currently, I start the M4 from a booted A5
Linux. To avoid half of the clocks get turned of by the M4 clock driver,
I need to specify clk_ignore_unused. Beside that, peripherals have to be
enabled/disabled in a non conflicting manor in the device trees...

For the interrupt router in MSCM, it would be nice if the access could
be done an atomic way, which would avoid the use of a lock mechanism.
But I guess this is not possible, since peripherals only support
standard ldr/str...?

There is the SEMA4 module which provides hardware semaphores. I'm aware
of the hardware spinlock drivers (drivers/hwspinlock/), I started to
implement such a driver for Vybrid. But so far a grep through the kernel
does not show one usage of that framework... I guess we could add dt
support for that, so we can assign the locks to individual drivers.

I also plan to have a deeper look into remoteproc/rpmsg, not sure if
locking of shared peripherals is part (or planned to be part) of that
framework.

For the clock stuff, the problem is more complex: I guess the would need
some kind of master/slave definition, where we disallow the change of
the shared clocks for the slave.

If you are aware of patches/solutions, I'm happy to hear it...

--
Stefan


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