[PATCH 15/19] arm64: dts: exynos: Add MSHC dt node for Exynos5433
Chanwoo Choi
cw00.choi at samsung.com
Tue Dec 2 00:49:52 PST 2014
From: Jaehoon Chung <jh80.chung at samsung.com>
This patch adds MSHC (Mobile Storage Host Controller) dt node for Exynos5433
SoC. MSHC is an interface between the system the SD/MMC card.
Cc: Kukjin Kim <kgene.kim at samsung.com>
Cc: Mark Rutland <mark.rutland at arm.com>
Cc: Marc Zyngier <marc.zyngier at arm.com>
Cc: Arnd Bergmann <arnd at arndb.de>
Cc: Olof Johansson <olof at lixom.net>
Cc: Catalin Marinas <catalin.marinas at arm.com>
Cc: Will Deacon <will.deacon at arm.com>
Signed-off-by: Jaehoon Chung <jh80.chung at samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi at samsung.com>
Acked-by: Inki Dae <inki.dae at samsung.com>
Acked-by: Geunsik Lim <geunsik.lim at samsung.com>
---
arch/arm64/boot/dts/exynos/exynos5433.dtsi | 42 ++++++++++++++++++++++++++++++
1 file changed, 42 insertions(+)
diff --git a/arch/arm64/boot/dts/exynos/exynos5433.dtsi b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
index 5637086..fef9bbc 100644
--- a/arch/arm64/boot/dts/exynos/exynos5433.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynos5433.dtsi
@@ -52,6 +52,9 @@
i2c9 = &hsi2c_9;
i2c10 = &hsi2c_10;
i2c11 = &hsi2c_11;
+ mshc0 = &mshc_0;
+ mshc1 = &mshc_1;
+ mshc2 = &mshc_2;
};
cpus {
@@ -502,6 +505,45 @@
status = "disabled";
};
+ mshc_0: mshc at 15540000 {
+ compatible = "samsung,exynos7-dw-mshc-smu";
+ interrupts = <0 225 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x15540000 0x2000>;
+ clocks = <&cmu_fsys CLK_ACLK_MMC0>,
+ <&cmu_fsys CLK_SCLK_MMC0>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x40>;
+ status = "disabled";
+ };
+
+ mshc_1: mshc at 15550000 {
+ compatible = "samsung,exynos7-dw-mshc-smu";
+ interrupts = <0 226 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x15550000 0x2000>;
+ clocks = <&cmu_fsys CLK_ACLK_MMC1>,
+ <&cmu_fsys CLK_SCLK_MMC1>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x40>;
+ status = "disabled";
+ };
+
+ mshc_2: mshc at 15560000 {
+ compatible = "samsung,exynos7-dw-mshc-smu";
+ interrupts = <0 227 0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0x15560000 0x2000>;
+ clocks = <&cmu_fsys CLK_ACLK_MMC2>,
+ <&cmu_fsys CLK_SCLK_MMC2>;
+ clock-names = "biu", "ciu";
+ fifo-depth = <0x40>;
+ status = "disabled";
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts = <4 13 0xff01>,
--
1.8.5.5
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