[PATCH 1/1] gpio: mvebu: enable and use IRQ_GC_MASK_CACHE_PER_TYPE

[Linus Walleij]

On Wed, Oct 2, 2013 at 2:34 PM, Gerlando Falauto
<gerlando.falauto at keymile.com> wrote:

> Since we have now introduced mask_cache within irq_chip_type to also
> handle per-chip-type mask registers, convert gpio-mvebu driver to use
> this new pointer.
>
> Also enable IRQ_GC_MASK_CACHE_PER_TYPE to actually handle separate mask
> registers for all three SoC variants handled by this driver.
>
> This wll fix a bug where requesting (and triggering) both EDGE- and
> LEVEL- based IRQs causes the kernel to hang.
>
> Signed-off-by: Gerlando Falauto <gerlando.falauto at keymile.com>
> Cc: Simon Guinot <sguinot at lacie.com>
> Cc: Thomas Petazzoni <thomas.petazzoni at free-electrons.com>
> Cc: Grant Likely <grant.likely at secretlab.ca>
> Cc: Linus Walleij <linus.walleij at stericsson.com>
> Cc: Andrew Lunn <andrew at lunn.ch>
> Cc: Jason Cooper <jason at lakedaemon.net>
> Cc: Gregory Clement <gregory.clement at free-electrons.com>
> Cc: Sebastian Hesselbarth <sebastian.hesselbarth at gmail.com>
> Cc: Linus Walleij <linus.walleij at linaro.org>
> Cc: Andrew Lunn <andrew at lunn.ch>
> Cc: Arnd Bergmann <arnd at arndb.de>
> Cc: linux-arm-kernel at lists.infradead.org

Thomas/Gregory: can you comment on this patch?

Yours,
Linus Walleij