[PATCH v2] ARM: tlb: ASID macro should give 32bit result for BE correct operation
ben.dooks at codethink.co.uk
Tue Oct 8 17:37:58 EDT 2013
On 08/10/13 02:55, Kim Phillips wrote:
> On Mon, 7 Oct 2013 18:49:20 -0400
> Santosh Shilimkar<santosh.shilimkar at ti.com> wrote:
>> On Monday 07 October 2013 12:37 PM, Victor Kamensky wrote:
>>> On 7 October 2013 08:57, Ben Dooks<ben.dooks at codethink.co.uk> wrote:
>>>> On 07/10/13 17:48, Victor Kamensky wrote:
>>>> If you are booting on the Arndale board, is there a patch to mark
>>>> the relevant Exynos devices as BE capable?
>>> Arndale need massive fixes in their BSP layer to be endian agnostic
>>> ARM V7 platform. Unfortunate it is not as simple as with few others
>>> that already marked as BE capable.
>>> Please see
>>> Mostly it is __raw_xxx conversion to xxx_relaxed, but there are
> apologies if this was explained earlier in the thread, but what has
> __raw_xxx -> xxx_relaxed have to do with endianness? the relaxed
> accessor variants allow the compiler to reorder the instruction: it's
> got nothing to do with byte swapping the data, no?
the __raw have similar properties, however the readl/writel relaxed
are basically __raw with byte-swapping and no attempt to do any other
Thus I thought these would be the best ones to go for.
Ben Dooks http://www.codethink.co.uk/
Senior Engineer Codethink - Providing Genius
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