[PATCH 3/3] clk: tegra: T114: add DFLL DVCO reset control

[Peter De Schrijver]

On Fri, Jun 07, 2013 at 02:19:09PM +0200, Paul Walmsley wrote:
> Add DFLL DVCO reset line control functions to the CAR IP block driver.
> 
> The DVCO present in the DFLL IP block has a separate reset line,
> exposed via the CAR IP block.  This reset line is asserted upon SoC
> reset.  Unless something (such as the DFLL driver) deasserts this
> line, the DVCO will not oscillate, although reads and writes to the
> DFLL IP block will complete.
> 
> Thanks to Aleksandr Frid <afrid at nvidia.com> for identifying this and
> saving hours of debugging time.
> 
> Signed-off-by: Paul Walmsley <pwalmsley at nvidia.com>
> Cc: Aleksandr Frid <afrid at nvidia.com>
> Cc: Peter De Schrijver <pdeschrijver at nvidia.com>
Reviewed-by: <pdeschrijver at nvidia.com>

Cheers,

Peter.