[PATCH 09/13] clk: exynos5420: register clocks using common clock framework

[Andrew Bresticker]

Tomasz,

>> +     apll = samsung_clk_register_pll35xx("fout_apll", "oscclk",
>> +                     reg_base + 0x100);
>> +     bpll = samsung_clk_register_pll35xx("fout_bpll", "oscclk",
>> +                     reg_base + 0x20110);
>> +     cpll = samsung_clk_register_pll35xx("fout_cpll", "oscclk",
>> +                     reg_base + 0x10120);
>> +     dpll = samsung_clk_register_pll35xx("fout_dpll", "oscclk",
>> +                     reg_base + 0x10128);
>> +     epll = samsung_clk_register_pll35xx("fout_epll", "oscclk",
>> +                     reg_base + 0x10130);
>> +     ipll = samsung_clk_register_pll35xx("fout_ipll", "oscclk",
>> +                     reg_base + 0x10150);
>> +     kpll = samsung_clk_register_pll35xx("fout_kpll", "oscclk",
>> +                     reg_base + 0x28100);
>> +     mpll = samsung_clk_register_pll35xx("fout_mpll", "oscclk",
>> +                     reg_base + 0x10180);
>> +     rpll = samsung_clk_register_pll35xx("fout_rpll", "oscclk",
>> +                     reg_base + 0x10140);
>> +     spll = samsung_clk_register_pll35xx("fout_spll", "oscclk",
>> +                     reg_base + 0x10160);
>> +     vpll = samsung_clk_register_pll35xx("fout_vpll", "oscclk",
>> +                     reg_base + 0x10170);
>
> Are all those PLLs really PLL35xx? At least for VPLL and EPLL a PLL
> without the K factor looks a bit awkward.

No they are not...  EPLL and RPLL should be pll36xx, but the rest are pll35xx.

Thanks,
Andrew