[PATCH v2 1/8] clk: flag to use upper half of the register as change indicator

Linus Walleij linus.walleij at linaro.org
Fri Jun 7 07:46:32 EDT 2013

On Thu, Jun 6, 2013 at 9:08 PM, Heiko Stübner <heiko at sntech.de> wrote:

> There exist platforms, namely at least all Rockchip Cortex-A9 based ones,
> that don't use the paradigm of reading-changing-writing the register contents,
> but instead only write the changes to the register with a mask that indicates
> the changed bits.
> This patch adds flags and code to support the case where the lower 16 bit of
> hold the information and the upper 16 bit are used as mask to indicate the
> written changes.
> As hardware-specific flags should not be added to the common clk flags, the
> flags are added to gate, mux and divider clocks individually.
> Signed-off-by: Heiko Stuebner <heiko at sntech.de>
> +       if ((clk_gate_flags & CLK_GATE_MASK_UPPER_HALF) && bit_idx > 15) {
> +               pr_err("%s: bit_idx %d invalid\n", __func__, bit_idx);
> +               return ERR_PTR(-EINVAL);
> +       }

Now this looks *EXTREMELY* familiar to a patch just sent by Haojian
for HiSilicon.

"[PATCH v2 3/6] clk: divider: add CLK_DIVIDER_HIWORD_MASK flag"

What kind of coincidence is this? Are Rockchip and HiSilicon using
the same silicon IP or are they of a common origin? (It is a small
world after all.)

I think you two guys need to read each others patch sets closely
here. I'd like Haojian to look at Heiko's patches and Heiko to look
at Haojian's patches, just to make sure you're not actually writing
two drivers for the same hardware in the end.

Linus Walleij

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