[PATCH v2 2/5] clk: samsung: Add support to register rate_table for PLL3xxx
dianders at chromium.org
Mon Jun 3 16:58:24 EDT 2013
On Mon, Jun 3, 2013 at 8:25 AM, Tomasz Figa <t.figa at samsung.com> wrote:
> From what I understood in the documentation is that there is a set of
> recommended P, M, S (, K) tuples for each PLL and they are not dependent on
> input frequency - f_in and f_out are provided in the table just for reference
> to see the relation between output frequency and input frequency.
> I think we should ask some H/W engineer about that to make sure and choose the
> proper implementation, which will work properly for future cases, instead of
> ending with something that works just with current cases.
Hopefully you and Yadwinder can take this on? You probably have
better access to the right people to ask.
I did dig up my 4210 manual which actually has one place where it
shows two options for FIN of VPLL: 24MHz and 27MHz. They don't seem
to share any PMSK values that are the same.
It seems like the tables were generated by choosing a bunch of
frequencies that people would probably like to make and then finding
the best way to make that frequency (probably backed up by a bunch of
simulation and testing of that exact combination).
We have landed most of this series of patches (with a few
modifications to later patches to avoid adding a global alias)..
...but if you decided to go a different way we'll take your version of
course (either now with a revert / re-pick or when we rebase later).
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