[PATCH v2] ARM: v6: prevent gcc 4.5 from reordering extended CP15 reads above is_smp() test

Will Deacon will.deacon at arm.com
Tue Jul 30 11:04:32 EDT 2013

On Tue, Jul 30, 2013 at 12:32:06PM +0100, Paul Walmsley wrote:
> Commit 621a0147d5c921f4cc33636ccd0602ad5d7cbfbc ("ARM: 7757/1: mm:
> don't flush icache in switch_mm with hardware broadcasting") breaks
> the boot on OMAP2430SDP with omap2plus_defconfig.  Tracked to an
> undefined instruction abort from the CP15 read in
> cache_ops_need_broadcast().  It turns out that gcc 4.5 reorders the
> extended CP15 read above the is_smp() test.  This breaks ARM1136 r0
> cores, since they don't support several CP15 registers that later ARM
> cores do.  ARM1136JF-S TRM section 3.2.1 "Register allocation" has the
> details.
> So mark the extended CP15 read as clobbering memory, which prevents
> the compiler from reordering it before the is_smp() test.  Russell
> states that the code generated from this approach is preferable to
> marking the inline asm as volatile.  Remove the existing condition
> code clobber as it's obsolete, per Nico's post:
>     http://www.spinics.net/lists/arm-kernel/msg261208.html
> This patch is a collaboration with Will Deacon and Russell King.
> Signed-off-by: Paul Walmsley <paul at pwsan.com>
> Cc: Will Deacon <will.deacon at arm.com>
> Cc: Russell King <rmk+kernel at arm.linux.org.uk>
> Cc: Nicolas Pitre <nicolas.pitre at linaro.org>
> Cc: Tony Lindgren <tony at atomide.com>
> ---

Acked-by: Will Deacon <will.deacon at arm.com>


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