[PATCH v2] arm: Fix deferred mm switch on VIVT processors

[Marc Kleine-Budde]

On 07/19/2013 06:45 PM, Catalin Marinas wrote:
> As of commit b9d4d42ad9 (ARM: Remove __ARCH_WANT_INTERRUPTS_ON_CTXSW on
> pre-ARMv6 CPUs), the mm switching on VIVT processors is done in the
> finish_arch_post_lock_switch() function to avoid whole cache flushing
> with interrupts disabled. The need for deferred mm switch is stored as a
> thread flag (TIF_SWITCH_MM). However, with preemption enabled, we can
> have another thread switch before finish_arch_post_lock_switch(). If the
> new thread has the same mm as the previous 'next' thread, the scheduler
> will not call switch_mm() and the TIF_SWITCH_MM flag won't be set for
> the new thread.
> 
> This patch moves the switch pending flag to the mm_context_t structure
> since this is specific to the mm rather than thread.
> 
> Signed-off-by: Catalin Marinas <catalin.marinas at arm.com>
> Reported-by: Marc Kleine-Budde <mkl at pengutronix.de>
> Cc: Marc Kleine-Budde <mkl at pengutronix.de>
> Cc: <stable at vger.kernel.org> # 3.5+

Tested-by: Marc Kleine-Budde <mkl at pengutronix.de>

regards,
Marc

-- 
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