[PATCH RFC 2/8] clk: sunxi: register factors clocks behind composite

[Maxime Ripard]

Hi Emilio,

On Mon, Jul 22, 2013 at 10:01:06PM -0300, Emilio López wrote:
> This commit reworks factors clock registration to be done behind a
> composite clock. This allows us to additionally add a gate, mux or
> divisors, as it will be needed by some future PLLs.

Thanks for this patch, it looks fine.

I'm actually wondering if we could do this as well for the mux/gate/div
that we have?

This way, we would cover all the cases, and could only have one clock
defined per actual hardware clock.

Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com
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