[PATCH V2 1/5] gpio: clean up gpio-ranges documentation
linus.walleij at linaro.org
Mon Jul 22 18:31:45 EDT 2013
On Mon, Jul 15, 2013 at 8:40 PM, Stephen Warren <swarren at wwwdotorg.org> wrote:
> This change makes documentation of the the gpio-ranges property shorter
> and more succinct, more consistent with the style of the rest of the
> document, and not mention Linux-specifics such as the API
> pinctrl_request_gpio(); DT binding documents should be OS independant
> where at all possible.
This is all good.
> This change also removes any mention of the #gpio-range-cells property.
> Such properties are useful when one node references a second node, and
> that second node dictates the format of the reference. However, that is
> not the case here; the definition of gpio-ranges itself always dictates
> its format entirely, and hence the value #gpio-range-cells must always
> be 3, and hence there is no point requiring any referenced node to
> include this property.
> Signed-off-by: Stephen Warren <swarren at nvidia.com>
Can this mention the newly introduced Backus-Naur Form
description of the ranges.
> Patches 2-6 need to be applied in the same branch, since they all build
> upon each-other.
Still waiting for the OF maintainers to ACK so can't apply this. :-(
> +It is useful to represent which GPIOs correspond to which pins on which pin
> +controllers. The gpio-ranges property described below represents this, and
> +contains information strucutres as follows:
speling of strucutres
Should you mention that this is given in BNF?
Or is that implicit for all bindings?
> -This makes it logical to let gpio drivers announce their pin ranges to
> -the pin ctrl subsystem and call 'pinctrl_request_gpio' in order to
> -request the corresponding pin before any gpio usage.
> + gpio-range-list ::= <single-gpio-range> [gpio-range-list]
> + single-gpio-range ::=
> + <pinctrl-phandle> <gpio-base> <pinctrl-base> <count>
> + gpio-phandle : phandle to pin controller node.
> + gpio-base : Base GPIO ID in the GPIO controller
> + pinctrl-base : Base pinctrl pin ID in the pin controller
> + count : The number of GPIOs/pins in this range
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