[PATCH V2 01/12] spi/mxs: Always set LOCK_CS

[Fabio Estevam]

On Tue, Apr 2, 2013 at 8:18 PM, Marek Vasut <marex at denx.de> wrote:
> Dear Trent Piepho,
>
>> There are two bits which control the CS line in the CTRL0 register:
>> LOCK_CS and IGNORE_CRC.  The latter would be better named DEASSERT_CS
>> in SPI mode.
>>
>> LOCK_CS keeps CS asserted though the entire transfer.  This should
>> always be set.  The DMA code will always set it, explicitly on the
>> first segment of the first transfer, and then implicitly on all the
>> rest by never clearing the bit from the value read from the ctrl0
>> register.
>>
>> The only reason to not set LOCK_CS would be to attempt an altered
>> protocol where CS pulses between each word.  Though don't get your
>> hopes up if you want to do this, as the hardware doesn't appear to do
>> this in any sane manner.
>
> Can you please elaborate on this part above? The description is very vague.
>
> Fabio, can you review this too please?

Sure, it would be nice if Trent could resend this series and copy the
SPI maintainer, Mark Brown.