[PATCH 2/4] clk: exynos-audss: allow input clocks to be specified in device tree

[Padmavathi Venna]

From: Andrew Bresticker <abrestic at chromium.org>

This allows the input clocks to the Exynos AudioSS block to be specified
via device-tree bindings.  Default names will be used when an input clock
is not given.  This will be useful when adding support for the Exynos5420
where the audio bus clock is called "sclk_maudio0" instead of "sclk_audio0".

Signed-off-by: Andrew Bresticker <abrestic at chromium.org>
Reviewed-on: https://gerrit.chromium.org/gerrit/57833
Reviewed-by: Simon Glass <sjg at chromium.org>
---
 .../devicetree/bindings/clock/clk-exynos-audss.txt |   31 ++++++++++++++++++-
 drivers/clk/samsung/clk-exynos-audss.c             |   28 +++++++++++++++--
 2 files changed, 53 insertions(+), 6 deletions(-)

diff --git a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
index 3115930..66d4662 100644
--- a/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
+++ b/Documentation/devicetree/bindings/clock/clk-exynos-audss.txt
@@ -16,6 +16,21 @@ Required Properties:
 
 - #clock-cells: should be 1.
 
+Optional Properties:
+
+- clocks:
+  - pll_ref: Fixed rate PLL reference clock, parent of mout_audss. "fin_pll"
+    is used if not specified.
+  - pll_in: Input PLL to the AudioSS block, parent of mout_audss. "fout_epll"
+    is used if not specified.
+  - cdclk: External i2s clock, parent of mout_i2s. "cdclk0" is used if not
+    specified.
+  - sclk_audio: Audio bus clock, parent of mout_i2s. "sclk_audio0" is used if
+    not specified.
+
+- clock-names: Aliases for the above clocks. They should be "pll_ref",
+  "pll_in", "cdclk", and "sclk_audio", respectively.
+
 The following is the list of clocks generated by the controller. Each clock is
 assigned an identifier and client nodes use this identifier to specify the
 clock which they consume. Some of the clocks are available only on a particular
@@ -38,15 +53,27 @@ pcm_bus         8
 sclk_pcm        9
 adma            10      Exynos5420
 
-Example 1: An example of a clock controller node is listed below.
+Example 1: An example of a clock controller node using the default input
+	   clock names is listed below.
+
+clock_audss: audss-clock-controller at 3810000 {
+	compatible = "samsung,exynos5250-audss-clock";
+	reg = <0x03810000 0x0C>;
+	#clock-cells = <1>;
+};
+
+Example 2: An example of a clock controller node with audio bus input clock
+	   specified is listed below.
 
 clock_audss: audss-clock-controller at 3810000 {
 	compatible = "samsung,exynos5250-audss-clock";
 	reg = <0x03810000 0x0C>;
 	#clock-cells = <1>;
+	clocks = <&clock 148>;
+	clock-names = "sclk_audio";
 };
 
-Example 2: I2S controller node that consumes the clock generated by the clock
+Example 3: I2S controller node that consumes the clock generated by the clock
            controller. Refer to the standard clock bindings for information
            about 'clocks' and 'clock-names' property.
 
diff --git a/drivers/clk/samsung/clk-exynos-audss.c b/drivers/clk/samsung/clk-exynos-audss.c
index 86d2606..39d3383 100644
--- a/drivers/clk/samsung/clk-exynos-audss.c
+++ b/drivers/clk/samsung/clk-exynos-audss.c
@@ -32,10 +32,6 @@ static unsigned long reg_save[][2] = {
 	{ASS_CLK_GATE, 0},
 };
 
-/* list of all parent clock list */
-static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
-static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };
-
 #ifdef CONFIG_PM_SLEEP
 static int exynos_audss_clk_suspend(void)
 {
@@ -64,6 +60,10 @@ static struct syscore_ops exynos_audss_clk_syscore_ops = {
 /* register exynos_audss clocks */
 void __init exynos_audss_clk_init(struct device_node *np)
 {
+	const char *mout_audss_p[] = {"fin_pll", "fout_epll"};
+	const char *mout_i2s_p[] = {"mout_audss", "cdclk0", "sclk_audio0"};
+	struct clk *pll_ref, *pll_in, *cdclk, *sclk_audio;
+
 	reg_base = of_iomap(np, 0);
 	if (!reg_base) {
 		pr_err("%s: failed to map audss registers\n", __func__);
@@ -81,10 +81,30 @@ void __init exynos_audss_clk_init(struct device_node *np)
 	clk_data.clk_num = EXYNOS_AUDSS_MAX_CLKS;
 	of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
 
+	pll_ref = of_clk_get_by_name(np, "pll_ref");
+	pll_in = of_clk_get_by_name(np, "pll_in");
+	if (!IS_ERR(pll_ref)) {
+		mout_audss_p[0] = __clk_get_name(pll_ref);
+		clk_put(pll_ref);
+	}
+	if (!IS_ERR(pll_in)) {
+		mout_audss_p[1] = __clk_get_name(pll_in);
+		clk_put(pll_in);
+	}
 	clk_table[EXYNOS_MOUT_AUDSS] = clk_register_mux(NULL, "mout_audss",
 				mout_audss_p, ARRAY_SIZE(mout_audss_p), 0,
 				reg_base + ASS_CLK_SRC, 0, 1, 0, &lock);
 
+	cdclk = of_clk_get_by_name(np, "cdclk");
+	sclk_audio = of_clk_get_by_name(np, "sclk_audio");
+	if (!IS_ERR(cdclk)) {
+		mout_i2s_p[1] = __clk_get_name(cdclk);
+		clk_put(cdclk);
+	}
+	if (!IS_ERR(sclk_audio)) {
+		mout_i2s_p[2] = __clk_get_name(sclk_audio);
+		clk_put(sclk_audio);
+	}
 	clk_table[EXYNOS_MOUT_I2S] = clk_register_mux(NULL, "mout_i2s",
 				mout_i2s_p, ARRAY_SIZE(mout_i2s_p), 0,
 				reg_base + ASS_CLK_SRC, 2, 2, 0, &lock);
-- 
1.7.4.4