[PATCH 03/10] ARM: fixup_pv_table bug when CPU_ENDIAN_BE8
ben.dooks at codethink.co.uk
Mon Jul 1 07:04:01 EDT 2013
The fixup_pv_table assumes that the instructions are in the same
endian configuration as the data, but when the CPU is running in
BE8 the instructions stay in little-endian format.
Make sure if CONFIG_CPU_ENDIAN_BE8 is set that we do all the
alterations to the instructions taking in to account the LDR/STR
will be swapping the data endian-ness.
Since the code is only modifying a byte, we avoid dual-swapping
the data, and just change the bits we clear and ORR in.
Note, not tested against an actual bug, it looked wrong.
Signed-off-by: Ben Dooks <ben.dooks at codethink.co.uk>
arch/arm/kernel/head.S | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/arch/arm/kernel/head.S b/arch/arm/kernel/head.S
index 8bac553..56ddd47 100644
@@ -594,8 +594,14 @@ __fixup_a_pv_table:
1: ldr ip, [r7, r3]
+ @ in BE8, we load data in BE, but instructions still in LE
+ bic ip, ip, #0xff000000
+ orr ip, ip, r6, lsl#24
bic ip, ip, #0x000000ff
orr ip, ip, r6 @ mask in offset bits 31-24
str ip, [r7, r3]
2: cmp r4, r5
ldrcc r7, [r4], #4 @ use branch for delay slot
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