[PATCH v2 18/27] arm: plat-orion: add more flexible PCI configuration space read/write functions
jgunthorpe at obsidianresearch.com
Mon Jan 28 14:51:11 EST 2013
On Mon, Jan 28, 2013 at 07:56:27PM +0100, Thomas Petazzoni wrote:
> However, with the usage of the emulated PCI host bridge and emulated
> PCI-to-PCI bridges, this is not the case: bus number 0 is the emulated
> bus on which the emulated PCI-to-PCI bridges sit, so from the Linux
> point of view, the real busses start at bus 1, but from a hardware
> point of view, they start at bus 0.
Hum.. This is a bit funny sounding, can you confirm..
The bus number programmed into all the end points must match the Linux
number. Ie the PCI-E Link Description register of end point devices
must report the same bus number as Linux. PCI-E devices learn their
bus number by capturing the bus number from type 0 configuration
For the most part config transactions issued to the PCI-E controllers
should be type 0 transactions with a bus number that matches what
Linux is setting.
The only time I think you'd ever see bus number 0 is when accessing
the config space of the Marvell PCI-E controller end port. But, I also
think you can avoid doing these transactions by just accessing the MMIO
versions of those registers..
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