L1 & L2 cache flush sequence on CortexA5 MPcore w.r.t low power modes

[Antti P Miettinen]

From: Lorenzo Pieralisi <lorenzo.pieralisi at arm.com>
> On Fri, Feb 22, 2013 at 09:04:04AM +0000, Antti P Miettinen wrote:
>> This did not get answered - are TLB fetches by sibling cores treated in
>> the same way as cache fetches? If core A has C bit cleared, is the cache
>> still available for TLB fetches by core B?
> 
> Yes, it is as long as the SMP bit is set in ACTLR.
> 
> Lorenzo

Thanks Lorenzo. Do you know if there are any known errata that would
invalidate any of the assumptions disussed in this thread?

--
Antti P Miettinen
http://www.iki.fi/~ananaza/