[BUG] v7_coherent_kern_range broken on big.LITTLE
Jon Medhurst (Tixy)
tixy at linaro.org
Fri Feb 15 07:06:25 EST 2013
On Fri, 2013-02-15 at 10:33 +0000, Lorenzo Pieralisi wrote:
> On Fri, Feb 15, 2013 at 10:04:37AM +0000, Jon Medhurst (Tixy) wrote:
> > On Thu, 2013-02-14 at 17:16 +0000, Will Deacon wrote:
> > > Hi Tixy,
> > >
> > > On Thu, Feb 14, 2013 at 05:07:43PM +0000, Jon Medhurst (Tixy) wrote:
> > > > The function v7_coherent_kern_range uses the macro icache_line_size to
> > > > read the current CPUs icache line size for the purpose of invalidating
> > > > all cache lines in the given range.
> > > >
> > > > Unfortunately, on the TC2 big.LITTLE test chip, the A15 icache line size
> > > > is 64 bytes, but the A7 size is only 32 bytes. So when the function
> > > > executes on the A15 it will miss out every alternate cache line for the
> > > > A7.
> > >
> > > There is a signal (IMINLN) to the core which allows A15 to behave as though
> > > it has a 32-byte line size and this should be driven correctly for big/little.
> > How do we set that signal? Is that something we have to set up in Linux
> > or is it something that we expect the Firmware to set up?
> If I am not mistaken, SCC register at offset 0x400 (bit 7) allows IMINLN to
> be forced to 0 (ie Instruction Cache minimum line size == 32 bytes).
> This can be done through board.txt so that it is set up as we want.
According to the TRM for TC2 the default value for that register is
0x33330c80, so adding the line "SCC: 0x400 0x33330c00" and incrementing
TOTALSCCS does the trick, and the A15's now report an icache size of 32.
We'll have to get everyone with a TC2 to make that change then?
As this is a TC2 issue, and not Linux related, shall we drop
linux-arm-kernel from all future replies to avoid the noise? I've added
linaro-dev to the cc list so this continues to get public visibility.
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