[PATCH v3 1/3] ARM: Introduce atomic MMIO modify

Jason Gunthorpe jgunthorpe at obsidianresearch.com
Fri Aug 30 16:08:30 EDT 2013

On Fri, Aug 30, 2013 at 11:03:42AM +0100, Catalin Marinas wrote:

> > Perhaps we should just bit the bullet and define relaxed accessors for all
> > architectures? It's not difficult to default them to the non-relaxed
> > variants if the architecture doesn't provide an optimised implementation.
> Yes, an asm-generic default relaxed would be good (that's what I
> suggested earlier in this thread and it was discussed in the past). But
> no-one volunteered ;).

Something I've always been confused about..

Do these _relaxed operators on ARM differ from the PCI-X definition of
relaxed ordering, and are they expected to generate a PCI TLP with
the relaxed ordering bit set?

If so, what does writel_relaxed do? RO has no effect on transactions
travelling away from the PCI host bridge, so it is useless for the
CPU to generate RO TLPs.

AFAIK, on x86 read_relaxed is expected to cause the PCI behavior.
Documentation/DocBook/deviceiobook.tmpl seems to confirm this.

It seems important to reconcile the meaning before standardizing these
things :)


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