[PATCH 09/18] ASoC: Samsung: Do not queue cyclic buffers multiple times

[Linus Walleij]

On Sun, Aug 11, 2013 at 7:59 PM, Tomasz Figa <tomasz.figa at gmail.com> wrote:

> The legacy S3C-DMA API required every period of a cyclic buffer to be
> queued separately. After conversion of Samsung ASoC to Samsung DMA
> wrappers somebody made an assumption that the same is needed for DMA
> engine API, which is not true.
>
> In effect, Samsung ASoC DMA code was queuing the whole cyclic buffer
> multiple times with a shift of one period per iteration, leading to:
>   a) severe memory waste - up to 13x times more DMA transfer descriptors
>      are allocated than needed,
>   b) possible memory corruption, because further cyclic buffers were out
>      of the original buffers, due to the offset.
>
> This patch fixes this problem by making the legacy S3C-DMA API use the
> same semantics as DMA engine (the whole cyclic buffer is enqueued at
> once) and modifying users of Samsung DMA wrappers in cyclic mode to
> behave appropriately.
>
> Signed-off-by: Tomasz Figa <tomasz.figa at gmail.com>
> Acked-by: Linus Walleij <linus.walleij at linaro.org>

If patch 1 thru 9 are uncontroversial now, maybe Vinod can apply
these for v3.12 so we can get less noise and risk of collissions
in the next merge window?

Just an idea.

Yours,
Linus Walleij