[PATCH] KVM: ARM: ignore guest L2 cache control SMCs on Highbank and OMAP

[Marc Zyngier]

On 2013-08-14 10:22, Andre Przywara wrote:
> Guest kernels with CONFIG_L2X0 set (for instance Highbank or OMAP4)
> will trigger SMCs to handle the L2 cache controller (PL310).
> This will currently inject #UNDEFs and eventually stop the guest.
>
> We don't need explicit L2 cache controller handling on A15s anymore,
> so it is safe to simply ignore these calls and proceed with the next
> instruction.
>
> Signed-off-by: Andre Przywara <andre.przywara at calxeda.com>

Hold on.

Are you trying to run A9 guests on KVM? Sorry, but that's not a 
supported mode of operation just yet.

So, until we have a proper framework to deal with multiple CPUs, the 
only valid configuration is A15-on-A15.

> ---
>  arch/arm/kvm/handle_exit.c | 20 ++++++++++++++++++++
>  1 file changed, 20 insertions(+)
>
> diff --git a/arch/arm/kvm/handle_exit.c b/arch/arm/kvm/handle_exit.c
> index df4c82d..2cbe6a0 100644
> --- a/arch/arm/kvm/handle_exit.c
> +++ b/arch/arm/kvm/handle_exit.c
> @@ -50,8 +50,28 @@ static int handle_hvc(struct kvm_vcpu *vcpu,
> struct kvm_run *run)
>  	return 1;
>  }
>
> +/*
> + * OMAP4 and Highbank machines do a SMC call to handle the L2 cache
> + * controller. They put 0x102 in r12 to request this functionality.
> + * This is not needed on A15s, so we can safely ignore it in KVM 
> guests.
> + */
> +static int kvm_ignore_l2x0_call(struct kvm_vcpu *vcpu)
> +{
> +	unsigned long fn_nr = *vcpu_reg(vcpu, 12) & ~((u32) 0);
> +
> +	if (fn_nr == 0x102) {
> +		kvm_skip_instr(vcpu, kvm_vcpu_trap_il_is32bit(vcpu));
> +		return 1;
> +	}
> +
> +	return 0;
> +}

And what if I run mach-foo which uses r12 to request bar services from 
secure mode? Is it safe to ignore it? We need something much better than 
just testing random registers to guess what the guest wants.

>  static int handle_smc(struct kvm_vcpu *vcpu, struct kvm_run *run)
>  {
> +	if (kvm_ignore_l2x0_call(vcpu))
> +		return 1;
> +
>  	kvm_inject_undefined(vcpu);
>  	return 1;
>  }

         M.
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