[PATCH 1/2] ARM: dts: i.MX6: configure L2 cache data and tag latency

[Shawn Guo]

On Fri, Apr 26, 2013 at 10:13:55AM +0200, Dirk Behme wrote:
> Configure the data and tag latency for the L2 cache. This improves the
> system performance.
> 
> This configuration is taken from Freescale's kernel patch
> 
> "ENGR00153601 [MX6]Adjust L2 cache parameter" [1]
> 
> which does
> 
> writel(0x132, IO_ADDRESS(L2_BASE_ADDR + L2X0_TAG_LATENCY_CTRL));
> writel(0x132, IO_ADDRESS(L2_BASE_ADDR + L2X0_DATA_LATENCY_CTRL));
> 
> In this patch we are doing the same via the device tree.
> 
> Signed-off-by: Dirk Behme <dirk.behme at de.bosch.com>

Both applied, thanks.