[PATCH v2 02/14] ARM: OMAP: counter-32k: Select the CR register offset using the IP scheme.

[Hiremath, Vaibhav]

On Mon, Jul 09, 2012 at 16:12:15, Shilimkar, Santosh wrote:
> On Mon, Jul 9, 2012 at 2:20 PM, Vaibhav Hiremath <hvaibhav at ti.com> wrote:
> >
> >
> > On 7/6/2012 2:51 PM, Santosh Shilimkar wrote:
> >> From: R Sricharan <r.sricharan at ti.com>
> >>
> >> OMAP socs has a legacy and a highlander version of the
> >> 32k sync counter IP. The register offsets vary between the
> >> highlander and the legacy scheme. So use the 'SCHEME'
> >> bits(30-31) of the revision register to distinguish between
> >
> >
> > Just for my understanding, can we get further information on SCHEME
> > bit-fields? What kind of information we have it here.
> >
> > I may need this info to pass on to design team here.
> >
> Sure. You can refer to the OMAP4 TRM for the bit builds.
> SCHEME bit field tell you difference between a highlander
> and legacy IP as the patch says.
> 

Santosh,

Can you point to the section of OMAP4 TRM? 

I referred to both Public TRM and internal TRM, but both only did mention
"TI internal Data".

And as per code, we are not checking any value in 31-30 bit-fields, code 
just assumes that, non-zero value would be highlander IP. 

Thanks,
Vaibhav