tegra3 vSMP cpu hotplug and LP=>G & G=>LP switch

[Barry Song]

hi guys,
As tegra3 is using vSMP (Variable Symmetric Multiprocessing) arch,
there are 4 high-performance(G) cores and one low-power(LP) core. At
runtime, both cpu dynamic hotplug and dynamic LP/G swith are used in a
real tegra3 product as a DVFS way to save power. kernel log in EeePad:
*cpu dynamic hotplug*
<4>[104626.426957] CPU1: Booted secondary processor
<7>[104627.427412] tegra CPU: force EDP limit 720000 kHz
<4>[104627.427670] CPU2: Booted secondary processor
<4>[104628.537005] stop_machine_cpu_stop cpu=0
<4>[104628.537017] stop_machine_cpu_stop cpu=2
<4>[104628.537059] stop_machine_cpu_stop cpu=1
<4>[104628.537702] __stop_cpus: wait_for_completion_timeout+
<4>[104628.537810] __stop_cpus: smp=0 done.executed=1 done.ret =0-
<5>[104628.537960] CPU1: clean shutdown
<4>[104630.537092] stop_machine_cpu_stop cpu=0
<4>[104630.537172] stop_machine_cpu_stop cpu=2
<4>[104630.537739] __stop_cpus: wait_for_completion_timeout+
<4>[104630.538060] __stop_cpus: smp=0 done.executed=1 done.ret =0-
<5>[104630.538203] CPU2: clean shutdown
<4>[104631.306984] tegra_watchdog_touch

*G<->LP switch*
<3>[104666.799152] LP=>G: prolog 22 us, switch 2129 us, epilog 24 us,
total 2175 us
<3>[104667.807273] G=>LP: prolog 18 us, switch 157 us, epilog 25 us,
total 200 us
<4>[104671.407008] tegra_watchdog_touch
<4>[104671.408816] nct1008_get_temp: ret temp=35C
<3>[104671.939060] LP=>G: prolog 17 us, switch 2127 us, epilog 22 us,
total 2166 us
<3>[104672.938091] G=>LP: prolog 18 us, switch 156 us, epilog 24 us,
total 198 us

Related codes don't exist in both http://nv-tegra.nvidia.com/gitweb
and kernel org, any people know the address to locate these kernel
source codes?

Thanks
barry