[PATCH 2/2] ARM: IOMMU: Tegra30: Add iommu_ops for SMMU driver

Joerg Roedel joerg.roedel at amd.com
Tue Jan 24 06:04:44 EST 2012

On Tue, Jan 24, 2012 at 10:57:01AM +0100, Hiroshi Doyu wrote:
> > Why do you completly ignore the size parameter in this function (and
> > in the unmap part below)?
> > According to the page-sizes you export to the generic layer size can be
> > 4k or 4M. You need to take care of that in this function.
> I'll drop 4MB support here once. I'll make another patch for 4MB page
> support later.

Okay, so when you only export 4k everything should be fine.

> > Hmm, this looks like there is a 1-1 mapping between hardware SMMU
> > devices and domains. This is not consistent with IOMMU-API semantics
> > where a domain can contain devices behind different SMMUs. Please fix
> > that.
> I'm a bit confused with the concept of "domain". I thought that
> "domain" is equivalent to a "virtual address space". Usually a IOMMU
> device provides a virtual address space for multiple client
> devices. IOW, a IOMMU device provides a virtual address space, which
> can be shared with multiple client devices.
> Actually Tegra SMMU case, a single IOMMU device has 4 different
> virtual address speace("smmu_as"). Each "smmu_as" has its own virtual
> address space. "smmu_as[i]" has mutiple "smmu_client" devices.
>   smmu_as[i] == domain[i]
> I don't understand why "a domain can contain devices behind different
> SMMUs" because those client devices belong to different virtual
> address spaces, and they should belong to different "domains".
> Could you please explain a bit more about "domain"?

A domain is, as you said, a virtual address space for IO devices. But
the important point is, an arbitrary number of devices can be part of a
domain. This also means that the devices can be behind different
hardware SMMUs. In this case your driver needs to program the page-table
pointer into more than one SMMU to give devices behind different SMMUs
the same address space.


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