[PATCH v6 9/9] ARM: vexpress: Add Device Tree for V2P-CA15 core tile (TC1 variant)

[Rob Herring]

On 01/19/2012 07:27 AM, Pawel Moll wrote:
> On Tue, 2012-01-10 at 14:21 +0000, David Vrabel wrote:
>> On 15/12/11 14:02, Pawel Moll wrote:
>>> This patch adds Device Tree file for the CoreTile Express A15x2
>>> (V2P-CA15) with Test Chip 1.
>>
>> This doesn't work as-is with the software model as accessing some of the
>> peripherals that aren't modeled will cause an exception.  Is it worth
>> having a device tree file suitable for the models? Or are the models too
>> configurable for this to be workable?
> 
> The model as you have it doesn't exactly represent the board for a
> number of reasons, mainly because there was no hardware design when the
> model was created, so some of the solution was best-guessed by the model
> people. Anyway, current A15 model can't be considered a 1-to-1
> equivalent of the VE board. The plan is that the models will be shipped
> with their own DTSes. I'll work on that in the following months, I can
> keep you updated (and use as a beta tester ;-) if you want.
> 
>>> As the chip's GIC has 160 interrupt inputs and equivalent SMM
>>> (FPGA) has GIC synthesised with 256 interrupts, NR_IRQS is
>>> increased.
>>>
>> [...]
>>> --- /dev/null
>>> +++ b/arch/arm/boot/dts/vexpress-v2p-ca15-tc1.dts
>> [...]
>>> +	memory at 80000000 {
>>> +		device_type = "memory";
>>> +		reg = <0x80000000 0x40000000>;
>>> +	};
>>
>> If CONFIG_ARM_ATAG_DTB_COMPAT is enabled the device tree will end up
>> with two nodes describing the memory ("memory" and "memory at 80000000" in
>> this case).
> 
> You're right - the skeleton.dtsi contains "memory" mode... Funnily
> enough originally I was using that name, but then Rob Herring suggested
> changing it to @80000000, which seemed reasonable.
> 
> Now I wonder - is the "memory" node special and should not contain
> "@address", or the skelton shouldn't contain the empty "memory" node...
> 

Hummm... I guess you should just use "memory" if you are using
skeleton.dtsi.

Rob