[PATCH] ARM: mx28: Clear CLKGATE bit prior to changing DIV field

[Dong Aisheng-B29396]

> -----Original Message-----
> From: Fabio Estevam [mailto:festevam at gmail.com]
> Sent: Thursday, January 19, 2012 11:58 AM
> To: Shawn Guo
> Cc: Lothar Waßmann; Estevam Fabio-R49496; w.sang at pengutronix.de;
> marek.vasut at gmail.com; linux-arm-kernel at lists.infradead.org;
> kernel at pengutronix.de; Guo Shawn-R65073; Dong Aisheng-B29396
> Subject: Re: [PATCH] ARM: mx28: Clear CLKGATE bit prior to changing DIV field
> Importance: High
> 
> 2012/1/19 Shawn Guo <shawn.guo at linaro.org>:
> 
> > My proposal is we need to clk_prepare_enable before clk_set_rate a
> > clock if the clock is gated, and then clk_disable_unprepare the clock
> > after clk_set_rate is done.  This applies whatever codes that want to
> > clk_set_rate a mxs clock.
> 
> So something like:
> 
> --- a/arch/arm/mach-mxs/clock-mx28.c
> +++ b/arch/arm/mach-mxs/clock-mx28.c
> @@ -809,6 +809,8 @@ int __init mx28_clocks_init(void)
>         clk_prepare_enable(&xbus_clk);
>         clk_prepare_enable(&emi_clk);
>         clk_prepare_enable(&uart_clk);
> +       clk_prepare_enable(&saif0_clk);
> +       clk_prepare_enable(&saif1_clk);
> 
>         clk_set_parent(&lcdif_clk, &ref_pix_clk);
>         clk_set_parent(&saif0_clk, &pll0_clk); @@ -822,6 +824,8 @@ int __init
> mx28_clocks_init(void)
>          */
>         clk_set_rate(&saif0_clk, 24000000);
>         clk_set_rate(&saif1_clk, 24000000);
> +       clk_disable_unprepare(&saif0_clk);
> +       clk_disable_unprepare(&saif1_clk);
> 
>         clkdev_add_table(lookups, ARRAY_SIZE(lookups));
> ---
> 
> didn't work on my tests (probe of mxs-saif fails with the same timeout message).
> 
> However if I use the clk_disable versions:
> 
> +       clk_disable(&saif0_clk);
> +       clk_disable(&saif1_clk);
> 
> Then it works fine.
> 

It looks strange to me.
Is there any big difference between clk_disable and clk_disable_unprepare for MXS?
Why clk_disable works?

Regards
Dong Aisheng