OMAP3 L2/outer cache enabled in kernel (after being disabled by uBoot)?

[Russell King - ARM Linux]

On Tue, Jan 17, 2012 at 09:27:02PM +0100, Shilimkar, Santosh wrote:
> There is nothing fancy here. It's an ARM security architecture feature
> which OMAP implements. Have given enough reason about boot-loaders
> issues.

There is nothing fancy about not being permitted to access registers
due to security restrictions.  What is fancy is that every SoC vendor
out there implements their own private API to provide a method to access
these registers without any form of commonality.

> Is OMAP getting beaten up here just because it uses ARM security
> feature and implements it's mechanics?

To confirm what Nicolas said in reply to this - I really don't care
either what kind of SoC this is.  This is purely about the technical
problems with what is being proposed.

And, as I've said several times already, the root cause of this problem
is not the SoC vendors, but a lack of standardization about how these
services are provided.

Imagine this: what if every vendor of a PC out there provided their
ACPI data in totally different formats?