[PATCH] ARM: clock-mx28: Fix end of loop condition

[Fabio Estevam]

On 1/17/12, Fabio Estevam <festevam at gmail.com> wrote:
> On 1/16/12, Fabio Estevam <festevam at gmail.com> wrote:
>
>> I will make more tests to confirm and post a new patch.
>
> On my tests I am always getting the BUSY bit of HW_CLKCTRL_SAIF0 as 1,
> no matter the timeout I add.
>
> BUSY bit is bit 29 of this register and matches the mx28 reference
> manual description.
>
> Looking at the Freescale kernel this BUSY bit is defined as 1 instead.

Not really, I looked at the wrong register.

The issue can be solved by clearing CLKGATE bit prior to writing to
DIV field, as described in the mx28 reference manual.

Just sent the updated patch that allows audio to work on mx28.

Regards,

Fabio Estevam