[PATCH v2 00/15] Make SMP timers standalone

[Marc Zyngier]

On 05/01/12 11:13, Shilimkar, Santosh wrote:
> On Thu, Jan 5, 2012 at 12:08 PM, Marc Zyngier <marc.zyngier at arm.com> wrote:
>> On 05/01/12 00:00, Linus Walleij wrote:
>>> However IIRC this situation does not occur in the ARM reference
>>> designs, notably Versatile Express since it simply isn't designed to
>>> be power-agressive in this way and does not gate the clock or
>>> power down the CPU power domain, it's always on, always
>>> clocked (albeit with shifting frequency).
>>>
>>> The Vexpress seem to register a clockevent for its SP804
>>> timer, and even though I've never used this machine I guess
>>> it would tick a few ticks during boot and then as TWD is
>>> registered it switches to that (due to higher .rate) and
>>> no IRQ is ever fired on the SP804 again.
>>>
>>> Does this correspond to what is seen in /proc/interrupts
>>> on the Vexpress?
>>
>> Yes. You get about 8 ticks worth of SP804, and then switch to TWD for good.
>>
>>> And does the system really work if you simply delete the
>>> code registering the SP804 clockevent from
>>> mach-vexpress/ct-ca9x4.c?
>>
>> No, because you need the global timer to calibrate the TWD on this
>> platform. But on the VE with a Cortex-A15 tile, the system works
>> perfectly with the architected timers being the only one in the system
>> (the SP804 is left unconfigured).
>>
>> But now that your cpufreq-aware patches are in -next, I can boot a Panda
>> without a single tick of the global timer (OMAP4 provides the "smp-twd"
>> clock).
>>
> That's only because CPUIDLE low power states are not enabled. You
> do that and without global timer, system will just die

Global timer is still present, configured and enabled. The kernel just
happens to select TWD as a better timer. Should TWD be turned off,
gp_timer will be selected again.

This is also what happens with the current implementation, and my
patches don't change that.

	M.
-- 
Jazz is not dead. It just smells funny...