[PATCH] ARM: vfp: Fix up exception location in Thumb mode

[Dave Martin]

Hi,

On Fri, Jan 14, 2011 at 8:10 AM, Catalin Marinas
<catalin.marinas at arm.com> wrote:
> On Fri, 2011-01-14 at 12:02 +0000, Russell King - ARM Linux wrote:
>> On Fri, Jan 14, 2011 at 11:43:04AM +0000, Catalin Marinas wrote:
>> > >        pr_debug("VFP: bounce: trigger %08x fpexc %08x\n", trigger, fpexc);
>> > >
>> > >        /*
>> > > +        * If the exception occured in thumb mode, pc is exception location + 2,
>> > > +        * the middle of the 32-bit VFP instruction.  Add 2 to get exception
>> > > +        * location + 4, the same we get in ARM mode.
>> > > +        */
>> > > +#ifdef CONFIG_ARM_THUMB
>> > > +       if (regs->ARM_cpsr & PSR_T_BIT)
>> > > +               regs->ARM_pc += 2;
>> > > +#endif
>> >
>> > You can use "if (thumb_mode(regs))" and avoid the #ifdef entirely.
>>
>> I don't think this is correct.  On entry to the undefined instruction
>> handler, we get the uncorrected PC value, so PC points to the
>> instruction after the faulting instruction.
>>
>> If it was an ARM instruction, that is located at PC-4.  If it was a
>> Thumb instruction, it is located at PC-2.  This PC value is passed
>> unmodified to the VFP entry code, and the passed r2 reflect the
>> value in regs->ARM_pc.
>
> The entry-armv.S code adds 2 to the r2 register in case of a 32-bit
> Thumb instruction, so it is no longer the same as the ARM_pc.
>
> Since the VFP instructions in Thumb mode are always 32-bit, Colin's
> patch made sense to me.

Is the comment preceding __und_usr_unknown causing some confusion here?

/*
 * The FP module is called with these registers set:
 *  r0  = instruction
 *  r2  = PC+4
 ...

That reflects the ARM case only: for Thumb, r2 is always PC+2 (?)

The comment at the start of do_undefinstr() (which receives these
registers) is correct though:

	/*
	 * According to the ARM ARM, PC is 2 or 4 bytes ahead,
	 * depending whether we're in Thumb mode or not.
	 * Correct this offset.

Cheers
---Dave