[PATCH v3 0/4] Introduce hardware spinlock framework
ohad at wizery.com
Tue Jan 4 07:23:20 EST 2011
On Sat, Dec 18, 2010 at 2:53 AM, Tony Lindgren <tony at atomide.com> wrote:
> * Ohad Ben-Cohen <ohad at wizery.com> [101216 13:34]:
>> Tony, Andrew, can you please have a look ?
>> Any comment or suggestion is appreciated.
> Looks sane to me from omap point of view and it seems the locks
> are now all timeout based:
> Acked-by: Tony Lindgren <tony at atomide.com>
Can you please have a look at this patch set (see link no.  below) ?
This hwspinlock framework adds support for hardware-based locking
devices, needed to accomplish synchronization and mutual exclusion
operations between remote processors that have no alternative
mechanism to do so.
This patch set adds a framework and an OMAP implementation. It had
circulated several times in the relevant mailing lists, and all
comments were addressed. The third version of this patch set  was
submitted about a month ago and so far there is no outstanding
Users for this framework that we are aware of:
1. OMAP4 and Davinci Netra (DM8168): both of these SoC have the same
hwspinlock module and will share the same host implementation.
2. Other platforms (such as omap3530 and omapl1xx) that have no such
hardware support, but would still need to achieve synchronization (to
communicate with their DSP).
The only way to achieve mutual exclusion on those platforms is by
using a shared-memory synchronization algorithm called Peterson's
We would still need the same hwspinlock framework for that - the busy
looping, the timeout, the various locking schemes, the lock resource
allocation - are all still valid. The only difference would be the
actual lock implementation, therefore we will add another host
for these platforms.
3. The C6474, a multi-core DSP device , have Linux running on one
of its cores, and hardware support for synchronization (btw the C6474
has a richer hardware module that would need more than the hwspinlock
framework offer today - it also supports queuing, owner semantics and
interrupt notification to let a processor know when it acquires a
lock, so it wouldn't have to spin..). Disclaimer: it will probably
take some time until c6x support is merged upstream, but this is
something that is being actively worked on .
Any comment or suggestion is appreciated.
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