[PATCH] ARM: EXYNOS4: Fix wrong pll type for vpll

[Kukjin Kim]

jhbird.choi at samsung.com wrote:
> 
> From: Jonghwan Choi <jhbird.choi at samsung.com>
> 
> Signed-off-by: Jonghwan Choi <jhbird.choi at samsung.com>
> ---
>  arch/arm/mach-exynos4/clock.c |    2 +-
>  1 files changed, 1 insertions(+), 1 deletions(-)
> 
> diff --git a/arch/arm/mach-exynos4/clock.c b/arch/arm/mach-exynos4/clock.c
> index 851dea0..0b39860 100644
> --- a/arch/arm/mach-exynos4/clock.c
> +++ b/arch/arm/mach-exynos4/clock.c
> @@ -1160,7 +1160,7 @@ void __init_or_cpufreq exynos4_setup_clocks(void)
> 
>  	vpllsrc = clk_get_rate(&clk_vpllsrc.clk);
>  	vpll = s5p_get_pll46xx(vpllsrc, __raw_readl(S5P_VPLL_CON0),
> -				__raw_readl(S5P_VPLL_CON1), pll_4650);
> +				__raw_readl(S5P_VPLL_CON1), pll_4650c);
> 
>  	clk_fout_apll.ops = &exynos4_fout_apll_ops;
>  	clk_fout_mpll.rate = mpll;
> --
> 1.7.0

Hi,

OK, will apply.

But would be helpful understanding if you could add git message in detail
like following...
"The PLL4650C is used for VPLL on EXYNOS4 so should be fixed"...I will add
this when apply.

Thanks.

Best regards,
Kgene.
--
Kukjin Kim <kgene.kim at samsung.com>, Senior Engineer,
SW Solution Development Team, Samsung Electronics Co., Ltd.