facing undefined inconsistent cache issues on cortex-a9

[Woodruff, Richard]

> From: linux-arm-kernel-bounces at lists.infradead.org [mailto:linux-arm-kernel-
> bounces at lists.infradead.org] On Behalf Of Shilimkar, Santosh

> > > Does this work if disable L1D as well on the processor you are running
> Linux ??
> > >
> > If we disable the L1 DCache we are never able to boot.
> > But this might be a different problem.
> >
> > If we disable ICache and leave DCache on it is much more stable, and
> > I think it might be related to timing issue in the data path.
> >
> For me, it seems that Cache isn't invalidated properly which leads to this
> issue.
> May be you can report the complete crash-log which can give more idea on the
> issue.

If you are unable to boot with dcache off then maybe your memory controller or memory part has timing issues.  Cache on will trigger burst accesses using different timings.  Such an early failure is more likely an issue outside of the arm unless you are doing something really odd.

Regards,
Richard W.