L2 cache support for pxa16x

[Eric Miao]

On Fri, May 21, 2010 at 7:07 PM, Haojian Zhuang
<haojian.zhuang at gmail.com> wrote:
>> diff --git a/arch/arm/mach-mmp/aspenite.c b/arch/arm/mach-mmp/aspenite.c
>> index a2d307e..d047d8c 100644
>> --- a/arch/arm/mach-mmp/aspenite.c
>> +++ b/arch/arm/mach-mmp/aspenite.c
>> @@ -17,6 +17,7 @@
>>  #include <linux/mtd/partitions.h>
>>  #include <linux/mtd/nand.h>
>>
>> +#include <asm/hardware/cache-tauros2.h>
>>  #include <asm/mach-types.h>
>>  #include <asm/mach/arch.h>
>>  #include <mach/addr-map.h>
>> @@ -125,6 +126,7 @@ static struct pxa3xx_nand_platform_data
>> aspenite_nand_info = {
>>
>>  static void __init common_init(void)
>>  {
>> +       tauros2_init();
>>        mfp_config(ARRAY_AND_SIZE(common_pin_config));
>>
>
> Why do you initialize L2 at here? I think that we should enable L2 a
> bit earlier. For example, in pxa168_init().
>

I think that's what dove is doing.